Exemplary embodiments relate to a nonvolatile memory device and, more particularly, to a bit line precharge circuit and a nonvolatile memory device including the same.
In a known semiconductor circuit or a known memory device, current consumption may sharply increase in a specific operation. For example, in the refresh operation of DRAM and in the precharge operation of a nonvolatile memory device, current consumption can sharply increase. The nonvolatile memory device is described below as an example.
To write data into a memory cell of the nonvolatile memory device, a program operation is performed. The program operation may be performed by supplying a program pulse to the memory cell according to an incremental step pulse program (ISPP) method, and a verification operation may be performed for every pulse by checking whether the memory cell has been programmed. If, as a result of the check, the memory cell has been programmed, the memory cell is treated as being a program pass. However, if, as a result of the check, the memory cell has not been programmed, a next program pulse is supplied to the memory cell.
Such a verification operation can be classified into a bit line precharge period, an evaluation period, and a sense period. In the bit line precharge period, a lot of current consumption is generated because all bit lines have to be precharged. Thus, a drop in power results because of a peak current. Such a drop in power influences the overall operation of the nonvolatile memory device, which has an effect on an internal clock thereby potentially causing trouble.
As described above, in the known nonvolatile memory device, a large amount of current may be consumed when a lot of bit lines are precharged at the same time. Accordingly, a drop in power may result thereby negatively affecting the operation of the known nonvolatile memory device.